Electronics Design

The overall electonics design is shown in the figure below. Analog and digital elcectonics are located in separate portions of a single physical box, with a shield layer between the analog and digital portions.

Digital Electronics:The XRT digital electronics architecture has four main functional blocks, the Instrument Control Processor, the Event Recognition Processor, the Clock Generator board, which controls the CCD readout waveforms, and the S/C interface board.

ICP (Instrument Control Processor): CUBIC used an 80C86 processor to perform all instrument control and event processing functions. In order to deal with the much higher readout rate of the XRT camera, we have split these functions into two separate processors. Because we want to retain as much of the CUBIC code as possible, and in order to minimize the number of processor types in the instrument, we have chosen to use identical 80C486 boards manufactured by SEI for both the Instrument Control Processor (ICP) and the Event Recognition Processor (ERP). The ICP board will be configured as the master, with the ERP board configured as a slave. This board utilizes VxWorks.

The ICP will be responsible for the following tasks: processing spacecraft commands; monitoring source flux and adjusting the CCD readout mode as required; monitoring housekeeping and checking for out-of-bounds conditions; transferring housekeeping and science data through the MIL-1553 bus to the spacecraft central memory and Solid State Recorder, respectively; calculating centroids of new bursts; and transmitting centroid positions and spectra to the ground through the TDRSS link.

Event Recognition Processor: The Event Recognition Processor (ERP) is responsible for digesting the data from the XRT camera. Its function is to reduce the data volume by a factor of 50-100 by identifying valid X-ray events on the basis of their morphology, and storing only the X-ray events in the science data stream. The processor will use the CUBIC event recognition algorithm, with two improvements: the "neighborhood" size will be increased from 3 x 3 to 5 x 5, and a full bias map will be used for bias subtraction.

Clock generator: The camera control/clock generator board controls the CCD camera and data interface. It will be based on our CUBIC and laboratory CCD camera designs. The clock generator is a DSP-based state generator utilizing a rad-hard Analog Devices AD-21020. The logic levels produced by the Clock Generator drive the Clock Driver board, which in turn generates the analog CCD clocking voltages.

CCD Driver: The CCD drivers provide the signals needed to clock data out of the CCD, converting the digital bit patterns produced by the Clock Generator board to the analog waveforms the CCD requires. All of the CCD bias voltages (both clock voltages and DC bias voltages) are programmable by ground command to accommodate any flat band shifts during the mission. Voltages of up to 15V must drive capacitances of up to 5nF with rise and fall times of less than 1us for the Image and Storage section clocks. The readout register clocks must drive capacitances of 60pF with 100ns rise and fall times.

Two clock driver circuits are being evaluated. One possible candidate is a pair of the hybrids developed for JET-X. These have at least 10 krads radiation tolerance, and already procured to the required quality level. The second candidate is the driver circuit developed at Penn State for CUBIC. The selection of clock drivers will be made in Phase B.

S/C Interface: The SCI board provides the interface to the S/C bus. In addition to hosting the MIL-1553 remote terminal, this board contains logic that decodes several special XRT commands to provide a hardware reset function and to capture the spacecraft time signal and synchronize the XRT clock with the spacecraft clock. This board also buffers both input and output data to provide a clean hardware interface to the on-board software.

Analog Electronics: The analog electronics will be based on the circuits flown on CUBIC and XMM/EPIC. With the exception of the clock drivers, which reside in the digital electronics box, the remaining boards are isolated from the digital electronics in order to minimize noise pickup.

Preamps: The preamps are based on the XMM/EPIC design. They will be housed inside the CCD camera to minimize noise pickup. The camera headboard contains 2 preamplifiers, which are AC coupled to the two output nodes of the CCD. In order to achieve the necessary slew rates and noise performance PMI OP37 preamps are used in non-inverting configuration with a gain of around X16. A noise figure of better than 5 e^- rms has been achieved at system level with this front-end.

Signal Chain: The signal chain electronics is responsible for extracting the CCD signal packets from the video output of the detector, using a correlated double sampling processor. A Phase B trade will be performed to select between the clamp/sample signal chain used by PSU on CUBIC and the gated integrator signal chain used by LU on EPIC. The signal chain board will be located in the analog electronics box. CCD data and housekeeping are digitized by a 12 bit ADC and passed to the ERP.

Power Supplies: The XRT power supplies consist of three major units: DC/DC converters, the TEC power supply, and the Heater Control unit.

DC/DC converters: The XRT will use COTS DC/DC converters to produce the following voltages: +/- 15V, +/- 5V, +5V (digital), and +32V. All DC/DC converters will provide isolation between the primary power and secondary power. The input and output of the converters are heavily filtered to prevent conducted EMI from the instrument and to reduce the spikes and ripple in the output voltage. The most critical voltages in the instrument have further linear regulation to reduce noise to extremely low levels. Power supply efficiencies are over 78%, based on measurements of CUBIC supply efficiencies.

TEC supply: The Peltier cooler (TEC) will be powered by a variable voltage power supply, based on the supply we designed and built for CUBIC. The output voltage can be set by the Instrument Control Processor (ICP), either open-loop or closed-loop, to control the CCD temperature. The supply is heavily filtered on both input and output to minimize noise in both directions. Its measured efficiency is given in Table TBD.

Distribution/Harness: The instrument harness will be run outside the telescope tube and will be carefully constructed and baked out to avoid contamination of the X-ray telescope mirrors. The harness will consist of two parts: one will run from the electronics box to the rear of the telescope tube to carry the CCD camera control and data signals and the heater power for the rear tube. The other will run to the front end of the tube to carry heater power and telemetry signals to the mirrors and door. Critical signals, including all of the CCD clocks, are sent through twisted pairs to control video frequency inductive loops. Quiet analog, noisy analog (clocks), and digital signals are carried on separate shielded cables.

Grounding/Shielding philosophy: Grounding and shielding are critical to maintaining the low noise performance of our CCD camera, which must be sensitive to sub-millivolt signal levels and must have system noise of order microvolts. The general grounding philosophy for the analog electronics is a massively parallel grounding scheme designed to minimize inductive noise pickup at video frequencies. The analog and digital electronics grounds are tied together at the ADC to eliminate ground loops that could introduce digital noise into the analog electronics system. All shields are grounded to the chassis at one end only in order to eliminate ground loops through the shields. This philosophy has been used successfully on ASCA, Chandra/ACIS, CUBIC, and XMM/EPIC to achieve system noise below 1 electron rms when referenced to the detector output amplifier.